In the figures, each element indicated by a reference numeral will be indicated by the same reference numeral in every figure in which that element appears. The first two digits of any four digit reference numerals and the first digit of any two or three digit reference numerals indicates the first figure in which its associated element is presented.
This invention relates in general to random access memory (RAM) and relates more particularly to tightly coupled, low overhead built-in self-test (BIST) logic that tests for fabrication errors. By "tightly coupled" is meant that the logic is located physically within the RAM block and has access to internal RAM signals that are not usually accessible via pins on the edges of a RAM chip. Access to internal RAM signals is required to simplify the BIST logic required. By "low overhead" is meant that the BIST logic requires a small amount of chip area.
During fabrication of a RAM, various processing errors can result in undesired shorts and opens. Because RAM chips are often manufactured with state of the art linewidths and fabrication processes, these chips are particularly susceptible to the inclusion of shorts and opens.
A short between adjacent bits will force these two bits to assume the same binary values, even when data entered into these two bits are unequal. Shorts between a pair of adjacent word lines or a pair of adjacent bit lines are more common. A short between bit lines causes these bits to be equal in every word that is accessed. A short between two word lines forces two words to be accessed simultaneously.
Bit shorts and opens to power and ground nodes can cause a bit to be stuck to zero or stuck to one. When any of these events occurs in data bits of the RAM, these shorts and opens will produce faulty data. When any opens occur in address bits, only a subset of the physical memory can be accessed. When any shorts occurs in address bits, writing to the intended memory location will also cause undesired writes at another location. Thus, an address error can adversely affect data in two locations.
It is important to test RAM chips for each of these manufacturing errors. BIST logic can be much more efficient than a chip tester in testing a RAM chip because it has direct access to internal signals that are not directly accessible by the chip tester. Embeddible testing can always be run at high speed because it doesn't require high frequency output pins, which are often difficult to test. Additionally, non-embedded tests often require the application of multiple test vectors to the pins of a RAM chip to produce a single desired RAM access. Thus, testing via embedded BIST logic can be easier and can significantly increase fault coverage within a given period of time. Therefore, embeddable built-in self-test (BIST) can be an effective test for fabrication errors.
FIG. 1 illustrates a typical random access memory core 11 and its associated input/output (I/O) circuits 12-14 and BIST logic 15-17. The I/O circuits include a memory data register (MDR) 12, a memory address register (MAR) 13 and an address decoder 14. The BIST logic includes BIST address generation logic 15, control logic 16 and data generation logic 18 and a data comparator 17. This comparator compares data generated by data generation logic with the data in MDR 12.
The RAM test sequence consists of a first phase of writing data to the RAM and a second phase of reading this data from the RAM and comparing it with expected data. During the first phase, address generation logic 15 produces a first sequence of addresses and, for each generated address, data generation logic 16 produces a data word that is written to the location identified by the generated address. During the second phase, address generation logic 15 generates the same sequence of addresses and, for each generated address, a comparator 17 compares the data in the location identified by that address with the data predicted to be in that location by the combination of the previous data stored in the MDR and the data generation logic.
Previously, a variety of algorithms have been utilized to test for the assortment of shorts and opens that can occur. These algorithms include that proposed by Knaizuk and Hartmann (see, for example, John Knaizuk, Jr., et al, An Algorithm for Testing Random Access Memories, IEEE Transactions On Computers, April 1977, p. 114 and John Knaizuk, Jr. and Carlos R. P. Hartmann, An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories, IEEE Transactions On Computers, vol. C-26;, No. 11, November 1977, P. 1141) as well as checkerboard, walking 1's, walking 0's and write address algorithms.
The walking 1's algorithm is illustrated in FIG. 2 and the walking 0's algorithm is illustrated in FIG. 3. Because both of these patterns assure that nearby words are unequal, either of these algorithms is useful in detecting whether two nearby words are shorted together or whether two address bits are shorted together. However, because most bits in adjacent words are equal, there is a very low fault coverage for shorts between adjacent pairs of data bits unless the pattern is shifted and repeated.
The checkerboard algorithm is illustrated in FIG. 4. This algorithm is particularly useful in testing for shorts between bits that are immediately adjacent within the same word or across two words. However, it does not test for most other types of shorts such as single bit shorts between bits that are offset by .+-.1 bit location in immediately adjacent words. It does not test for word-length shorts between words spaced an even number of words apart. It also does not test for single bit address shorts that result in the same data being written to or read from addresses spaced an even number of words apart.
The write address algorithm, illustrated in FIG. 5, simplifies the identification of the addresses of two words that are stuck together. After writing into each location the address of that location, if the words at two addresses are shorted together, then both of these words will contain the same address. When an error is detected during the second phase of the RAM test sequence, an error will be detected at the location that does not contain its address.
Each of these algorithms has various strengths and weaknesses. For example, the write address makes it easy to identify which of pairs or sets of words are shorted together. However, it is poor at identifying single bit errors because, for most adjacent words, these two words will have the same bit values in most bit locations. Thus, for good fault coverage (i.e., for an ability to detect a high fraction of all possible RAM data storage errors), several different algorithms need to be implemented. Unfortunately, the implementation of several different RAM test algorithms requires an unreasonably large amount of cumbersome built-in logic.
Because there is little available room on a RAM chip for test circuitry, it is advantageous to implement a RAM test algorithm that does not require a large amount of chip area. In general, because the built-in self-test (BIST) circuitry is typically utilized either only as part of the manufacturing process or, during power up of a device to identify whether an included RAM chip is good or not. Additionally, in order to avoid undue time and expense in testing these chips, it is also important to have a shorts test. Thus, it is necessary to achieve as good or better fault coverage with BIST is done as with test vectors at the expense of as little logic as possible and in as little time as possible.
Using a BIST algorithm, a 50 ns, 1 megabit RAM can be fully loaded with a single pattern of data and checked for errors in a time approximately one two-hundredths of a second, assuming a 128 k.times.8 layout structure. However, for acceptable fault coverage, several different patterns need to be successively loaded into the RAM and the actual values of the stored data needs to be compared with the intended values to be stored. Such a test could therefore require several seconds.
Pseudorandom sequences, such as those generated by linear feedback shift registers (LFSRs), have been used to implement a variety of testing. However, these LFSR tests require a significant amount of chip area and/or exhibit a poor level of fault coverage for a given period of time.